1. Technical Field
Some embodiments of the present invention relate to inter-processor communication and, more specifically, to inter-processor communication using a handshake wrap around a communication interface between the processors.
2. Description of the Related Arts
Communication between two processors always presents the challenge of determining which processor will serve as the “master” and which will serve as the “slave.” Each processor executes its own set of instructions and may be in a busy or low power state while the other processor is attempting to communicate with it. Often, processors are embedded in a package and have a limited number of pins allotted thereto. Software handshaking presents special challenges to the communication hardware, e.g., buffers, and also results in increased power consumption due to the need for continuous readiness.
One solution has been to use two signals for handshaking between processors, such as is the case with RTS/CTS in RS232 protocol. This approach requires the use of two, instead of just one, general purpose input/output (“GPIO”) pins per processor. The use of two GPIO pins is clearly undesirable in view of the fact that, as discussed above, a limited number of pins are allotted to each processor. Another solution has been to use a single handshaking line that works from slave to master only. The handshaking from master to slave is implemented as query packets, the undesirable result of which is an increase in protocol overhead and power consumption in the slave interface due to the requirement that the slave processor remain in a constant state of readiness.
Therefore, what is needed is a mechanism for implementing handshaking between processors that is implemented via a single line and that does not require one of the processors to remain in a constant state of readiness.